<?xml version="1.0"?>

<!DOCTYPE owl [
	<!ENTITY rdf "http://www.w3.org/1999/02/22-rdf-syntax-ns#">
	<!ENTITY rdfs "http://www.w3.org/2000/01/rdf-schema#">
	<!ENTITY xsd "http://www.w3.org/2001/XMLSchema#">
	<!ENTITY owl "http://www.w3.org/2002/07/owl#">
	<!ENTITY cc "http://web.resource.org/cc/#">
	<!ENTITY project "http://ebiquity.umbc.edu/ontology/project.owl#">
	<!ENTITY person "http://ebiquity.umbc.edu/ontology/person.owl#">
	<!ENTITY pub "http://ebiquity.umbc.edu/ontology/publication.owl#">
	<!ENTITY assert "http://ebiquity.umbc.edu/ontology/assertion.owl#">
]>

<!--

This ontology document is licensed under the Creative Commons
Attribution License. To view a copy of this license, visit
http://creativecommons.org/licenses/by/2.0/ or send a letter to
Creative Commons, 559 Nathan Abbott Way, Stanford, California
94305, USA.

-->

<rdf:RDF 
		xmlns:rdf = "&rdf;"
		xmlns:rdfs = "&rdfs;"
		xmlns:xsd = "&xsd;"
		xmlns:owl = "&owl;"
		xmlns:cc = "&cc;"
		xmlns:project = "&project;"
		xmlns:person = "&person;"
		xmlns:pub = "&pub;"
		xmlns:assert = "&assert;">
	<pub:Article rdf:about="http://ebiquity.umbc.edu/paper/html/id/792/Realization-of-a-Novel-Fault-Tolerant-Reversible-Full-Adder-Circuit-in-Nanotechnology">
		<rdfs:label><![CDATA[Realization of a Novel Fault Tolerant Reversible Full Adder Circuit in Nanotechnology]]></rdfs:label>
		<pub:title><![CDATA[Realization of a Novel Fault Tolerant Reversible Full Adder Circuit in Nanotechnology]]></pub:title>
		<pub:publishedOn rdf:datatype="&xsd;dateTime">2010-07-01T00:00:00-05:00</pub:publishedOn>
		<pub:abstract><![CDATA[In parity preserving reversible circuit, the parity of the input vector must match the parity of the output vector. It renders a wide class of circuit faults readily detectable at the circuit’s outputs. Thus reversible logic circuits that are parity preserving will be beneficial to the development of fault tolerant systems in nanotechnology. This paper presents an efficient
realization of well known Toffoli gate using only two parity preserving reversible gates. The minimum number of garbage
outputs and constant inputs required to synthesize a fault tolerant reversible full adder circuit has also been given. Finally,
this paper presents a novel fault tolerant reversible full adder circuit and demonstrates its superiority with the existing
counterparts.]]></pub:abstract>
		<pub:booktitle><![CDATA[Int. Arab J. Inf. Technol.]]></pub:booktitle>
		<pub:publisher><![CDATA[Int. Arab J. Inf. Technol.]]></pub:publisher>
		<pub:author>
			<rdf:List>
				<rdf:first>
					<person:Person rdf:about="http://ebiquity.umbc.edu/person/html/et al./"><person:name><![CDATA[et al.]]></person:name><rdfs:label><![CDATA[et al.]]></rdfs:label></person:Person>
				</rdf:first>
				<rdf:rest>					<rdf:List>
						<rdf:first>
							<person:Person rdf:about="http://ebiquity.umbc.edu/person/html/Muhammad/Rahman"><person:name><![CDATA[Muhammad Mahbubur Rahman]]></person:name><rdfs:label><![CDATA[Muhammad Mahbubur Rahman]]></rdfs:label></person:Person>
						</rdf:first>
						<rdf:rest rdf:resource="&rdf;nil" />
					</rdf:List>
				</rdf:rest>
			</rdf:List>
		</pub:author>
		<pub:firstAuthor>
<person:Person rdf:about="http://ebiquity.umbc.edu/person/html/et al./"><person:name><![CDATA[et al.]]></person:name><rdfs:label><![CDATA[et al.]]></rdfs:label></person:Person>
		</pub:firstAuthor>
	</pub:Article>

<rdf:Description rdf:about="">
	<cc:License rdf:resource="http://creativecommons.org/licenses/by/2.0/" />
</rdf:Description>

</rdf:RDF>
